US20050046717A1 - Synchronization protocol - Google Patents

In a seventh aspect the present invention provides a monolithic image sensing device including an image processor, the integrated circuit being configured to operate in a system having a host processor, the image processor being configured to receive, from the host processor, a request for access to a next available frame of image data from a framestore; in the event the frame of image data is available, sending a message to the host processor indicative of the image data's availability; and in the event the frame of image data is not available, waiting until it is available and then sending a message to the host processor indicative of the image data's availability. The second prior art suffers the following problems. This operation is repeated for all the columns in the sensor array Always clocked—see also section Clocking. In order to operate the sensor in the normal mode the following steps are be followed:. The image region read function of Callisto allows the user to read all the pixel values out of a defined rectangular region of the unprocessed image in a single operation. This section lists the acronyms, abbreviations and similar information used in this specification.

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The selectable capacitor structure used in the PGA. The compensation structure used in the PGA opamp. The floorplan of the ADC.

The block diagram of the ADC. Timing diagram of the ADC in the normal mode. Dynamic range expansion window. Incomplete dynamic range expansion window. General Callisto message format. Register access message format. Callisto command message format. Register data message format. Command data message format. Command data format for processed image read command.

Frame sync message format. Frame store write message format. Unprocessed image read command message. Processed image read command with arguments. Processed image read command without arguments. Sub-sampled image read command with arguments. Sub-sampled image read command without arguments.

Sub-pixel read command message. Command execution and frame store write states. Frame store buffer locking. Image sensor data interface timing. Image sensor timing signals. Image sensor timing—external capture. Serial interface synchronous timing: Serial interface synchronous timing single bite transfer from microprocessor to Callisto. Error recovery timing using break.

External register interface read timing. External register interface write timing. Four-byte Register Read Access. Register Write and Read Accesses. Direct Frame Store Write Sequence. Sub-functions of the Processed Image Read Function. New Fram events—Double buffering. Single Buffer—One missed frame. Double Buffering—Same cadence as normal operation for single buffer. Double Buffering—No missed frames, simultaneous read and write.

Double Buffering—One missed frame. Sub-sample Buffer RAM architecture. Symmetric FIR parallel implementation. Reuse of multiplier and adder tree. Block memory scheme decoupling decimation factors and filter order.

Reduced linestore 2D FIR. Tag image processing chain. First sample tag structure, showing symbol arrangement. First sample tag structure, showing macrodot arrangement, fully populated with macrodots. Second sample tag structure, showing symbol arrangement. Second sample tag structure, showing macrodot arrangement fully populated with macrodots.

The detailed description is broken down into sections for convenience. Section A describes a preferred embodiment of the present invention in the form of the Jupiter image sensor chip with on-board image processing.

Section B describes the functions of the Ganymede image sensor component of Jupiter. Section C describes the design of the Ganymede image sensor. Section E describes the functions and design of the Callisto image processor component of Jupiter.

Section F describes alternative filtering and subsampling circuits which may be utilised by Callisto. Section G describes netpage tag sensing algorithms adapted to utilise the Callisto image processor for tag image processing and tag decoding in the context of the netpage networked computer system outlined in the cross-referenced patent applications listed above. The preferred form of the invention is a monolithic image sensor, analog to digital converter ADC , image processor and interface, which are configured to operate within a system including a host processor.

It should appreciated that the aggregation of particular components into functional or codenamed blocks is not necessarily an indication that such physical or even logical aggregation in hardware is necessary for the functioning of the present invention. Rather, the grouping of particular units into functional blocks is a matter of design convenience in the particular preferred embodiment that is described.

The intended scope of the present invention embodied in the detailed description should be read as broadly as a reasonable interpretation of the appended claims allows. The Jupiter image sensor has been designed for high-speed low-cost machine vision applications, such as code sensing in devices such as the Netpage pen and Netpage viewer. Jupiter comprises an image sensor array, ADC function, timing and control logic, digital interface to an external microcontroler, and implementation of some of the computational steps of machine vision algorithms.

Jupiter 1 has two main functional blocks: Ganymede 4 and Callisto 6 blocks. Callisto comprises the image processing, image buffer memory, and serial interface to a host processor. A parallel interface 8 links Ganymede 4 with Callisto 6 , and a serial interface 10 links Callisto 6 with the host processor 2.

Jupiter has several internal and external interfaces. External interface include the host processor interface and a flash exposure and capture interface. Both of these interfaces belong to Callisto and are described in more detail in the Callisto section below. The internal interfaces in Jupiter are used for communication among the different internal modules.

The internal interfaces in Jupiter are described in more detail below. Each module in Jupiter has two power modes: The power is controlled via an internal 8-bit register. Each bit of this register is used to control one separate module.

A bit value of 0 means that the associated module is turned off while a bit value of 1 means that the associated module is turned on.

The packaging of Jupiter is performed using a wafer-level packaging technique to reduce the overall manufacturing cost. The physical placement of the pads and their dimensions, and the wafer-level die specifications, accommodate the wafer-level packaging process. As best shown in FIG. The sensor array comprises pixels 20 , a row decoder 22 , a column decoder and MUX The following table shows characteristics of the sensor array The ADC block is used to digitise the analog output of the sensor array.

The following table shows characteristics of the ADC: The following table shows characteristics of the PLL: The image sensor interface is used internally in Ganymede to read the image sensor data. The interface between Ganymede and Callisto represented by signals iclk, isync, ivalid, idata is described below in more detail.

The following table shows the image sensor interface pins: Name Function Type icapture This signal triggers a frame Digital input capture sequence. This signal may be used to start a conversion in the ADC. It should be noted that the number of clock pulses between events in all timing diagrams is for the purposes of illustration only. The actual number of clock cycles will vary depending upon the specific implementation.

The control and timing block 16 provides timing and control signals to the ADC The following table shows the ADC 26 pins. During this period the analog inputs are also valid. The period that it takes for the calibration to take place will depend on the particular architecture. The following table shows the pins of the clock multiplier.

The timing of the clock multiplier is shown in FIG. This interface controls the power state of the modules in Ganymede. Each module in Ganymede has a digital input pin, which turns the module on or off. This section describes the registers that are used in Ganymede. Note that Callisto's registers are described in Appendix E.

The address gaps between registers is intentional, to allow possible expansion during the design process, and also to facilitate the classification of registers and their functions.

The reset values correspond to us and 1. This register contains the offset error value obtained after a calibration cycle. This is a read-write register.

Upon read, this register is reset to 0. A value of 1 means that the circuit is off in sleep mode , and a value of 0 means that the circuit is on active mode. At any given time only one bit of this register shall be high. In this mode the start of the capture cycle is determined by the icapture signal.

The period of a capture cycle is determined by the period of the icapture signal. The normal operation, however, resumes if a new capture signal arrives after the current capture cycle. When RESETB is set low, and iclk is toggling, Ganymede and all its components are reset, and all registers are reset to predefined values. The reset cycle takes only one clock cycle of iclk. A CMOS process offers several different photodetector structures, almost all present as parasitic devices.

The main devices are photogate, vertical and lateral bipolar structures, and vertical and lateral diodes. The preferred structure was chosen mainly on the estimated sensitivity of that structure in the nm range.

Sensitivity is a function of several parameters:. Quantum efficiency dependent on junction profile. Effective detector area the effective area can be improved by using microlenses. Pixel capacitance which depends on the structure as well as the pixel circuits.

Among these, quantum efficiency plays a more important role in the selection of the structure, as the other two parameters are less dependent on the junction profile. This section describes the circuits used at each pixel. Here we only discuss the shuttered or freeze-frame pixel circuits, although unshuttered pixels can also be used Two circuits commonly used for a shutter pixel are shown in FIGS. The difference between the two circuits is the location of the reset transistor M 1 with respect to the storage node X.

In both circuits M 1 is the reset transistor, M 2 is the transfer transistor, M 3 is the output transistor, and M 4 is the row-select transistor. The capacitor Cs is the storage capacitance, which may implicitly exist as parasitic capacitances at the storage node X. Alternatively, additional capacitance can be added to improve the charge retention capability of the pixel.

Notwithstanding their differences, the circuits of FIGS. This is because during the active period of the pixel integration time shown in FIG. The main difference between operation of the two circuits is during the reset period of the read cycle. For the circuit of FIG. Also in the circuit of FIG. However, during the reset period of the circuit of FIG. A major problem faced by all active pixel circuits is the voltage drop when the reset voltage is lowered.

In shuttered pixels there is also the voltage drop induced by the transfer transistor. It should be noticed that this voltage drop reduces the dynamic range of the pixel, and therefore is an undesirable effect. The voltage drop is caused because of capacitive coupling between the gate of these transistors are the storage node.

Many alternatives have been suggested to remedy this problem, including increasing the reset voltage Vreset to account for the voltage drop, or using more complex read-out circuits. All of these alternatives bring their own set of undesirable side-effects. As shown, the storage node includes a capacitor, the other side of which is connected to txb, the logically negated version of tx. It will be appreciated that txb is a particularly convenient signal, in terms of timing and voltage, to use.

However, any other suitable signal can be used to partially or wholly compensate for the voltage drop. The value of the capacitor is determined such that it compensates for the substantially all of the voltage drop effects.

Physically the capacitor can be implemented such that it covers the active circuits, such that it does not affect the fill factor of the pixel. Compared to the total capacitance of fF, this is negligible, and therefore it does not affect the sensitivity of the pixel. The main parameters determining sensitivity are the QE, pixel area, and effective pixel capacitance. In order to simulate the sensitivity we use the circuit shown in Figure. The input current sources are ratioed to reflect their respective QE at a wavelength of nm.

In order to estimate the sensitivity we can use these values in a transient simulation. We use AC simulations. By applying an AC voltage at the storage node, and then measuring the drawn current, we can find an estimate for the total capacitance.

From the simulations the total capacitance at the storage node is 31 fF and 40 fF for the Nwell-Psub, and Pdiff-Nwell-Psub structures, respectively. The sensitivity of the devices can be calculated to be We have found that sensitivity improves only as a function of fill factor, and is relatively constant for pixel dimensions larger than 10 um.

A column circuit 30 , as shown in FIG. At the end of an integration cycle, the column circuit 30 is activated. The rows are sequentially multiplexed to the input of this circuit. The illustrated circuit performs buffering in addition to pixel level and column level correlated double sampling CDS. This circuit is advantageous over the traditional source-follower structure, as it provides a gain closer to one, and therefore reduces the dynamic range loss from the pixel.

The output of the first buffer is sampled twice, using two identical sample-and-hold structures. Then all pixels in the row are reset, and the reset value is sampled, this time onto the Cs capacitor. This operation performs the pixel level CDS. During the period when the sampling is performed, the cro signal is set high, and in effect resets the output buffer circuits following the nodes Xr and Xs.

Once sampling has finished, the cro signal is set low and the sampled signals are transferred to Xr and Xs, and buffered to the outputs. This operation performs column level CDS. The column decoder is part of the column circuit It implements a N- 2 N decoder, and as such it can be used in a random access mode. The timing of the signals controlling the pixel and column circuits can be separated into alternating integration and read-out cycles.

During each integration cycle 32 , the entire sensor array 12 is first reset and then the electronic shutter is left open to integrate the photocurrent. At the end of this cycle the shutter is closed and the integrated charge is stored in the pixel. In the read-out cycle 24 the stored charge is read out row by row and the pixel-level and column-level CDS is performed, and the output is read out pixel by pixel.

The timing diagram for the integration cycle 32 is shown in more detail in FIG. The main signals during this cycle are the reset and tx signals. These signals act on all pixels in the sensor array. The read-out cycle is more complex as it involves several different operations. In the next phase, the entire row of pixels is reset and the reset value is sampled and held by its associated capacitor. The row decoder circuit is designed such that it supports the resetting of only one row of pixels during the read-out cycle, while it globally resets the pixel array during the integration cycle.

The pixel CDS 40 is inherently done during this same cycle. This operation is repeated for all the columns in the sensor array At the same time, the reset and tx signals will take a global role and can be active on all rows. As the row decoder 44 implements a N- 2 N decoder, it can be used in a random access mode. The level shift buffer uses a basic feedback level shifter, which is properly ratioed to avoid any potential latch-up during fast transitions.

In this circuit except for the two inverters, all other transistors are designed with the high voltage option. Notice that output PMOS transistor 50 has been intentionally made weaker than NMOS 52 , to remove any possible overlap between the outputs from two consecutive rows when switching from one row to the next. The only circuits that require biasing are the column circuits There are four biasing voltages that need to be generated: The layout design of the sensor is described in this section.

The most important part of the layout design is the pixel design, and the interacting layouts surrounding the pixel array. A VSS ring, which also has the Psubstrate tap, surrounds the pixel array.

This is to ensure that the NMOS transistors within the pixel array receive the best possible substrate biasing, as there is no Psubstrate tap inside the pixels to conserve area. The layout of the pixel should be such that the effective photodetector area is maximised. In the following section we present the layout design of the four different pixel structures that have been selected as alternative candidates for use in the Jupiter design.

The photodiode is an NWell-Psub structure, including a central NWell connection, from which the silicide layer is removed except where the contact to M 1 is formed. The VCC supply voltage runs both horizontally and vertically to produce a mesh power structure, which reduces the impedance of the supply planes significantly. The read, reset, tx and txb signals run horizontally.

The out signal runs vertically. The capacitor has been highlighted in the figure. It is formed by the parasitic capacitance between M 4 and M 5. The bottom plate which is on M 4 is connected to the storage node through a set of stacked vias. For the specific value required for the capacitor, it turns out that the implemented capacitor covers all the active area of the transistors, and therefore it also provides a natural shield for these circuits.

The pixel is almost identical to that shown in FIG. There is no M 4 below the area where txb has been widened, and therefore no capacitance is formed. The layout is very similar to those using a photodiode. The pixel circuit is identical to that used in the photodiode based pixels, and therefore it will not be described here again. The Pdiff area in this case has been maximized to increase the emitter area. The silicide has been removed from the Pdiff area, except where the emitter contact is made.

A VSS ring which also has the Psubstrate taps surrounds the pixel array. This is to ensure that the NMOS transistors within the pixel array receive the best possible substrate biasing, as there is no Psubstrate tap inside the pixels. The VCC supply in the pixels runs both horizontally and vertically, to produce a low impedance supply mesh.

The power routing to the row and column decoders are provided using the top metal layers from M 3 to M 6. The most critical circuits in any image sensor that may be affected by the incoming light are the row and column driving circuits, simply because they are physically close to the pixel array and therefore will be exposed to light.

In order to avoid any potential problems, all the circuits in the current design are covered by metal layers. Notice that the design rules do not allow the use of a single continuous layer of metal, and therefore multiple overlapping metal layers have been used to cover the circuits in the preferred embodiment. Nevertheless, all circuits have been shielded in the preferred embodiment. The size and the number of pixels can be designed according to the required specification.

This section describes basic steps to operate the sensor. The image sensor only supports one operation mode, which is the normal mode. In order to operate the sensor in the normal mode the following steps are be followed:. The reset and tx signals should also be set to low, otherwise, the sensor may dissipate power. The selection of appropriate architecture for the ADC is a critical step in achieving reliable design, and silicon performance.

A fully differential pipelined ADC design is used in the preferred embodiment. A redundant signed digit RSD structure is used because it presents an inherent self-correcting function due to the redundant nature of the operation, and because it is relatively tolerant to offset error in comparators, which is the major source of error in other ADC structures. It consists of identical stages, each of which has an analog input, an analog residue output and two digital outputs.

If the input is between the two levels, the input is directly amplified. The RSD digital outputs from all stages are then converted to a two's complement number system. The ADC bit-slice can be implemented using switched capacitor circuits. In this approach the input to each stage is first sampled on two capacitors Cs sampling capacitor and Cf feedback capacitor.

At the same time the input is compared against two levels and the digital bits are extracted. In the second phase, the capacitors are connected to an opamp to form an amplifier with a gain of 2. For higher resolution ADCs more than 8 bits or for mixed signal designs, a differential approach is used, to reduce the effects of charge injection and substrate coupling. A critical component of the bit-slice is the operational amplifier The gain, speed, and power dissipation of the opamp determines the overall performance of the ADC.

A fully-differential folded-cascode structure was chosen for this design for the following reasons. Folded-cascode often does not require compensation.

The gain of a folded-cascode opamp can be improved using gain-boosting techniques. The optimization of the opamp is simpler due to the smaller number of transistors in the circuit. The biasing of the opamp can be varied without affecting the stability. Therefore, if a lower speed ADC is required the bias current can simply be reduced to lower the power dissipation.

Not shown in this Figure is the common-mode feedback circuit, which forces the common-mode voltage at the output nodes to a predefined value.

This circuit is simplified for illustrative purposes and does not represent the overall complexity involved in the design. In the following sections the design of each major component is described and the justifications for using a particular circuit are explained. The choice of the biasing voltages is very crucial. In general a trade-off between area size of bias transistors , and the power dissipation the bias currents should be made.

The role of the bias voltages in the opamp are as follows:. In the actual implementation the sizes of the transistors have been optimized such that the VDS voltages are always at least 0. This is to ensure that these transistors are always in the saturation region. The input current to the bias generator is provided by the reference current generator described below.

The common mode feedback circuit CMFB forces the outputs of the folded opamp to have a predefined common-mode voltage. This circuit effectively tries to change the biasing conditions through a feedback loop. The differential output of the opamp is used in a capacitive divider to find the common mode voltage of the output. This voltage is then fed back into two differential pairs, which control a current that is injected into the NMOS branch.

The other input of the differential pairs is connected to the common mode voltage VCM. This feedback mechanism effectively sets the common mode voltage at the output to VCM. The size of the capacitors Ccmfb in this circuit is only about 50 fF. The dynamics of the CMFB directly affects the dynamics of the opamp, and therefore during circuit optimization special attention should be paid to the CMFB circuit.

Also notice that the CMFB circuit has a different feedback loop, and therefore its dynamics are almost isolated from the dynamics of the opamp. In order to increase the gain of the folded cascode opamp, gain boosting stages are required. The overall gain of the folded cascode stage without gain boosting is less than This is because the cascode transistors have minimum length 0.

These amplifiers have been implemented such that they can be turned off. In addition to the power savings achieved by doing this, the output voltage when the circuit is disabled will be set to a value that turns off the transistor that it is connected to. For example, during the off period the output of the top opamp in the figure will be pulled high to Vdd, and therefore the PMOS transistor driven by the output will be turned off.

This turning off mechanism reduces the pressure on the voltage source used to set the common mode voltage at the output of the opamp. In fact when the gain boosting amplifiers are turned off, the output of the opamp will be floating, and the output can be set to any desired value.

An important point in the design of these stages is that their bandwidth should be much more than the overall bandwidth of the main opamp, as otherwise they will form additional poles in the circuit and reduce the phase margin. The bandwidth of the opamp has been designed to exceed MHz. For an N-bit pipeline ADC the required bandwidth is approximately. Therefore, a bandwidth of about 1 GHz is required for these amplifiers.

This in turn translated into a large biasing current. A relatively large proportion of the power in the ADC is consumed by these amplifiers. The clock generator 66 produces all the clock phases necessary for the operation of the ADC The circuit is essentially a two-phase clock generator, and extra clock phases are also generated. Each of these clock phases is used to control the sequence of events in the pipelined ADC.

Notice that the clock phases alternate between the stages of the ADC. As shown in FIG. This circuit requires a well controlled resistor. In order to maintain good control over the bias current against resistor tolerance the resistor in the preferred embodiment has been implemented as a digitally switched resistor ladder, as shown in FIG.

Each ladder consists of 16 equal resistors. The value of these resistors is chosen such that the total resistance in the middle of the ladder is equal to the required resistance. For each stage of the ADC two comparators are required. The switched capacitor structure 70 is followed by two cross coupled differential pairs 72 , which act as the main comparator stages.

The reason for using two stages is that the input capacitors are relatively small to reduce the loading on the opamps in the bit slice. This in turn dictates the use of smaller input transistors for the first stage, and therefore, the available gain from only one stage would be low. The second stage ensures that the overall gain is high enough to avoid meta-stable states. The output of output from differential pairs is passed to a latched RS flip-flop 74 , which ensures that the output does not change before and after the decision has been made, and also to make sure that the two outputs are always inverted, which may not be the case if a meta-stable state occurs.

In order to generate the common mode and reference voltages necessary for the operation of the ADC a common-mode generator is designed. The common mode voltage is derived from an inverter with self feedback. The advantages of this circuit are its simplicity, and automatic tracking of the supply voltage and process corners.

The switch is used to cut off the feedback during the sleep mode, to avoid power dissipation see FIG. An opamp-based circuit using resistors in the feedback loop is used to derive the Vrefp and Vrefn, as shown in FIG. The reference voltages Vrefp and Vrefn can be obtained as: For a reference voltage of 1. The Vref reference voltage is generated by a bandgap generator set to output 1. The opamps used in this circuit are based on a wide-range OTA design, to achieve medium gain and high stability in the presence of large capacitive loading.

Note that the Vrefp and Vrefn are used to as input to the opamp in the second phase of conversion. They are also heavily decoupled using large MOS capacitors to reduce the bouncing on these voltages. The circuit is shown in FIG. Miller compensation has been used to ensure stability. The current design is stable with capacitive loads of more than 30 pF. The bandgap generator produces the main reference voltage from which the Vrefp and Vrefn voltages are derived.

It is also used for generating the reference current used in the bias circuit. The resistor values have been chosen to produce an output voltage of approximately 1.

This means that the bandgap generator is in fact out of balance and the output voltage will be temperature dependent. This is in fact a desirable feature for this design. At higher temperatures the dynamic range or voltage swing of all circuits in the chip will reduce. Therefore, if the reference voltage is constant, the required dynamic range of circuits will be higher than what they can achieve.

For example, the dynamic range at the output of the image sensor will be lowered at higher temperatures. With a constant reference voltage, the reference levels for the ADC will be constant, and therefore, the ADC will be forced to provide more dynamic range than required. However, if the reference voltage has a negative temperature coefficient, then the biased circuits will be automatically adjusted to lower biasing currents and voltages, and the amount of dynamic range discrepancy will be reduced.

This choice is to increase the gain of the opamp and increase the supply rejection. Compensation is necessary in this opamp. A nested miller compensation has been used, to reduce the size of the compensation capacitors. At the input of the ADC a digitally programmable amplifier has been implemented.

This PGA can have gain values from 0. The structure uses a switched capacitor design. The simplified schematic diagram is shown in FIG. In the first phase the input is sampled onto capacitors Cs. Also other capacitors are precharged to known values. In the second phase the capacitors are connected to the opamp and form an amplifying stage. This particular structure has been chosen to facilitate correlated double sampling CDS in the image sensor. During CDS, in the first phase of the clock the signal value is present, and in the second phase the reset value.

The values are subsequently subtracted. The capacitor Cf in this design is fF. Capacitor Cs is a linearly selectable capacitor as shown in FIG. In this figure Cs 1 represents a unit capacitance of 50 fF. There are however, two main changes in this opamp. One is the use of larger transistors, mainly to increase the bandwidth of the opamp, and the other is the use of a basic miller compensation structure at the output branch, as shown in FIG.

The source of instability in the PGA is from several factors. The first is the larger gain-bandwidth product required in the opamp. This brings the poles at the output branch close to other poles in the circuit, such as those at the output of the gain boosting OTAs.

Also the size of the feedback capacitors is relatively small, to limit the total input capacitance when the gain is to its maximum. The compensation structure tries to bring the poles at the output of the gain boosting OTAs down, and also adds a zero by adding the series Rcomp resistor , to cancel one of the poles.

The outputs from the bit slices are generated in a pipeline. After 4 H lines After 5 H lines After 6 H lines After 7 H lines Model No.: The active duration of STH pulse is always one-pixel width. Page of Go. Table of Contents Add to my manuals Add. Page 9 Reproduction Center 0. Page 10 of a 25mm diameter area, with all display pixels set to a gray level, to the luminance of that same area when any adjacent area is driven dark.

Page 14 CN21, 22, 23, Page 16 - Model No.: Page 17 - 7. Page 20 There shall not be visible light from the back-lighting system around the edges of the screen as seen from a distance 50[cm] from the screen with an overhead light level of [lux].

Page 21 8 Shock test non-operating Pulse width: Page 23 - Page 24 Figure 3. Page 25 - Figure 5. Page 26 - Figure 6. Block Diagram - 1. Pin Description - 2. Page 34 - Memory Map Model No.: Page 37 - Reset Timing Model No.: Page 47 Timer 0: Page 48 - Model No.: Page 49 - Model No.: Page 50 The Baud rate in Mode 1 and Mode 3 can be determined by overflow rate of Timer 1, Timer 2 or both one for transmit and other for receive.

Page 54 - Model No.: Page 55 - Model No.: Page 58 The M has 3 programmable lock bits that when programmed according to Table will provide different levels of protection for the on-chip code and data. Page 60 XTAL1 signal. Page 61 - 8. Page 67 - Model No.: Page 68 - Model No.: Page 71 Data inversion control for odd pixel bus if more than half signals in the bus change state, this will be set. Page 75 - Model No.: Page 76 Display A port green data. Page 80 All timing is measured at 1.

Page 83 IHS falling edge. Page 86 The block diagram is depicted as follows: Page 97 Hstart and Hend. Page - Model No.: Page The programmable LPF can be used for noise-reduction. Page As shown in above table, there are 7 fields about the row based display attributes. Page Given by the flexibility of this mode, associated with SP code feature, it is already sufficient to create the window-like menu. Page In total, there are 15 possible line insertion encoded by this field.

Page The remaining codes represent the lines inserted between two display rows. Page 0, Blink, is still effective in the programmed blinking rate. Page However, if SPT bit is set, the background color will disappear and become transparent. Page Each dot in the graphic character font is encoded by three bits, which are corresponding to R, G, B colors. Page Bit 1, I, of character attribute. Page Frame Buffer. Page V and H respectively. Page OSD default setting for space code color Bit0: Page SOD operation.

Page horizontally the starting and ending pixels along the Mth line. Page The threshold of number of pixels that will be treated as an active line. Page 0, 1, till the final one entity Page Meanwhile the internal address pointer will be increased automatically. Page Vsync coming , will show on the Intensity pin. Page Bit 0 to Bit3. Page Data port of the OSD window register.

Page It is very important to know the programmed range for Window 1 and Window 2 must be covered by the original visible domain, defined by OSDStartRow and EOD bit setting for the last display row.

Page Defining the window shadow of window 4. Page Vsep0 Page HsyncOut; if the pulse of incoming Vsync is missing, an artificial pulse will be inserted with pulse width defined by VPW.

The radio portable terminal shown in FIG. This dual-mode microprocessor may further include an electrically erasable programmable ROM EEPROM which can be used for permanent storage of a program or data. The mode switch is connected to first-mode and second-mode select terminals not shown via a plurality of conductors The user interface is connected via a control input conductor to the microprocessor to provide the microprocessor with predetermined information. Specifically, the control input conductor provides means for starting the mode change between the first mode and the second mode in the dual-mode microprocessor The user interface is connected to the microprocessor by a plurality of data input lines and a plurality of data output lines It is understood from experiments that the level of noise generated in the dual-mode microprocessor can be reduced considerably when the microprocessor operates only in internal mode the aforementioned first mode where the individual internal memories , and are mainly used, as compared with a case where the microprocessor operates in external mode the second mode in which an external memory is used.

In the first prior art, therefore, the dual-mode microprocessor operates while being switched to a single-chip mode, i. Specifically, the basic operation is carried out in single-chip mode in which case noise to be generated by an operation to access an external device connected to the CPU or an external memory via an external bus is minimized.

When the microprocessor is operating in this single-chip mode, the ROM and RAM as external memories are inactive. Further, no signals are flowing through an external address bus and a data bus The level of noise to be generated is reduced by setting those external memories and external buses inactive and optimizing the time for which the microprocessor operates in single-chip mode. To reduce the level of noise generated by the microprocessor while the radio portable terminal is receiving radio data, the programs that are stored in the dual-mode microprocessor should be categorized.

More specifically, individual modules routines included in the programs are associated with the respective functions of the radio portable terminal by systematically analyzing the codes of each program.

Based on those functions, the modules can be separated into two main categories. The modules of the first category are associated with the functions that are susceptible to the influence of noise, e. The modules of the first category are executed inside the microprocessor when it is operating in single-chip mode. The modules of the second category are associated with the functions that are insusceptible to the influence of noise, such as the radio transmitting function, the function for changing the operation mode of the radio portable terminal and the function to communicated with a user.

The modules of the second category operate in extension mode using the ROM and RAM as external memories, the external address bus and the data bus To effectively use an additional memory which is provided by the internal RAM , the modules of the first category are further separated into a main algorithm and sub algorithms.

The main algorithm of the first category consists of an active program which runs continuously. The sub algorithms are programs which are called as needed and frequently use the external address bus, and each sub algorithm is formed by, for example, a delay loop or a loop which monitors a change in the status of the input or the like.

The software is designed in such a way that the main algorithm of the first category is permanently saved in the internal ROM EPROM of the microprocessor and the sub algorithms of the first category are stored first in the external memories and Each sub algorithm is transferred to the internal RAM every time it is called or only when its specific module is needed.

Once the module of any sub algorithm is loaded into the internal RAM , this sub algorithm is executed when the microprocessor returns to the single-chip mode or the internal mode. The first problem is the necessity of an exclusive CPU. The second problem lies in that the RAM should be of an exclusive type for the following reason. As a cache in a general-purpose CPU is capable of automatically caching a saved command or data, such a command or data in the incorporated cache is freely rewritten when an external memory is accessed.

This leads to the necessity of an exclusive RAM which prevents automatic rewriting of the contents of the cache. Another solution is to store a program commands or data in a non-cache area so that the program commands or data will not be cached. But, this scheme prevents the internal RAM from functioning as a cache in normal operation mode, the system's processing speed in normal operation mode is slowed. The third problem is that the CPU to be used itself becomes expensive because the CPU should be a special chip, not a general-purpose one, in order to avoid the first and second problems.

First, the performance gets lower as the reception speed becomes lower. That is, the second prior art is directed to a reception-only terminal and the operation clock is always reduced when the terminal is connected to a communication circuit to receive radio data.

More specifically, if this prior art is adapted to a terminal having both transmission and reception capabilities, the operation clock is decreased both in transmission mode and reception mode, the performance is significantly lowered.

Secondly, operation clocks are needed for two systems for the following reason. Most of general-purpose CPUs do not have two clock inputs, and the clocks of general-purpose CPUs which have two clock inputs are a normal operation clock and a clock for measuring the time.

The frequency of the time measuring clock is about 32 KHz, which is very slow as the reference clock for radio reception. The use of this clock leads to a considerable reduction in reception speed and is not therefore practical. In this case, an exclusive CPU equipped with another clock input becomes necessary. Thirdly, when the frequency of the reference clock is reduced or the reference clock is disabled at the time of radio reception, it takes time to return to the normal processing, resulting in a significant reduction in performance.

Further, reducing the frequency of the reference clock requires that the OS Operation System should handle control of the operation of the radio unit. Furthermore, this terminal may fail to properly receive reception data for the following reason. It takes time to adjust the timer or clock or time to stabilize the PLL Phase Locked Loop or crystal oscillator after the reduction of the clock frequency or the disabling of the reference clock, so that the reception operation cannot be initiated during such a time.

This leads to a significant reduction in performance. If the timer or the like in the OS gets wrong, the radio unit does not operate properly and some adjustment should be performed to set the radio unit in the proper operation. Such processing needs a considerable time to restore the normal reception operation, so that processing of received data may not be completed in time to catch the next data. First, this prior art copes only with the noise that is generated by the reference clock used in a radio section.

That is, while generation of noise by the CPU's access to the external bus is dominant in an actual radio portable terminal, the third prior art is directed to a measure against noise generated in the radio section and this method cannot cope with a radio portable terminal which has the radio section integrated with the CPU that performs transmission and reception of information. Secondly, the noise that is generated by the CPU's access to the external bus has a wide frequency band.

The frequency band of the noise generated by the CPU's access to the external bus has a width of several MHz, so that alight alteration of the reference clock cannot eliminate the influence of noise on the frequency band used in radio communication. Thirdly, some radio portable terminals do not make access synchronous with the reference clock. The timing for memory access is determined by the time, not based on the reference clock.

When the operation reference clock is changed, therefore, the timing for memory access is changed and the proper memory access may not be carried out. It is not therefore possible to significantly alter the operation clock of the system. Accordingly, it is a primary object of the present invention to provide a noise reducing method for a radio portable terminal, which stores an internal operation program that does not access an external memory in a cache incorporated in a CPU in synchronism with data received by radio, and allows the radio portable terminal to be operated only with access to the internal cache at the time of radio reception, thereby reducing access to the external memory, so that noise to received data can be reduced.

It is another object of this invention to provide a noise reducing method for a radio portable terminal, which can reduce noise by masking interruption to a CPU before a predetermined program is stored in an internal cache in the CPU, thereby suppressing rewriting of a program stored in the cache and preventing access to an external memory of the CPU.